Module 1
Evolution of 8086 family of microprocessors
– 8088 to Itanium, Internal architecture of 8086, block diagram, Registers,
flags, Programming model, 8086 and 8088, 8086 memory organization, segmented
memory, Physical address calculation, Memory Addressing, Addressing modes.
Lecture #1
1. Synopsis
·
Overview of 8085 microprocessor
·
Evolution of 8086 family of microprocessors
2. Target
By this
lecture, you should be aware of the following topics:
a)
The internal architecture of 8085
b)
The generation of x86 microprocessors.
3. Introduction
The 8085 was an 8-bit microprocessor
made by Intel in
the mid-1970s. It
was binary
compatible with the more-famous Intel 8080
but required less supporting hardware,
thus allowing simpler and less expensive
microcomputer systems to be built.
4. Revision/Prerequisites
Please refer to the
text Microprocesor architecture of Remesh Gaonkar-Fifth Edition and Advanced microprocessors and peripherals,
A K Ray & K M Chaudhari.
5. Concepts
CPU Architecture
The 8085 Architecture follows the von Neumann
architecture, with a 16bit address bus, and an 8bit data bus. But it is
actually based on Harvard concept.
Registers:
The 8085 can access 216 (= 65,536)
individual 8-bit memory locations, or in other words, its address space is 64
KB. Unlike some other microprocessors of its era, it has a separate address
space for up to 28 (=256) I/O ports. It also has a built in register
array which are usually labeled A(Accumulator), B, C, D, E, H, and L. Further
special-purpose registers are the 16-bit Program Counter (PC), Stack Pointer
(SP), and 8-bit flag register F. The microprocessor has three maskable
interrupts (RST 7.5, RST 6.5 and RST 5.5), one Non-Maskable interrupt (TRAP), and one
externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual
pins on the processor-a feature which permitted simple systems to avoid the
cost of a separate interrupt controller chip.
Buses:
Address bus - 16 line bus
accessing 216 memory locations (64 KB) of memory.
Data bus - 8 line bus accessing one 8-bit byte of data in one
operation. Data bus width is the traditional measure of processor bit
designations, as opposed to address bus width, resulting in the 8-bit microprocessor
designation.
Control buses - Carries the
essential signals for various operations.
Evolution of 8086 family of microprocessors – 8088 to Itanium
The x86 architecture first appeared as the Intel 8086 CPU
in 1978. The 8086 was a development of the Intel 8085 processor, and was created such
that programs written in assembly for the 8085 could be mechanically translated
to equivalent programs in 8086 assembler language.
This made the 8086 a tempting migration path for 8085 software vendors, but
not without significant redesign of the system hardware due to the 8086's
16-bit data bus. To address this Intel introduced the externally 8-bit 8088 processor. The 8088 could run 8086
software, but reduction in data pins (from 16 to 8) it was feasible to
interface it with existing 8-bit system chips.
From their fifth-generation chips onwards, Intel adopted the Pentium name for their x86 CPUs. The
architecture has twice been extended to a larger word size.
In 1985, Intel released the 32-bit 386 to replace the 16-bit 286. This
extension to the x86 architecture is commonly called IA-32
(an abbreviation for Intel Architecture, 32-bit), but is also
referred to as i386, x86-32, or simply Intel Architecture.
In 2003, AMD
further extended the architecture to 64 bits, variously called x86-64, AMD64 (AMD's branding, formerly AA-64
(an abbreviation for AMD Architecture, 64-bit)), Intel 64 (Intel's
branding, formerly EM64T or IA-32e) and x64 (Microsoft and Sun Microsystems' vendor-neutral naming
convention). Intel 64 should not be confused with the unrelated IA-64
architecture.
The table below lists historically significant x86 desktop processors
grouped by generation. Note that the definition of a CPU generation is somewhat
ambiguous; each manufacturer has their own timeline progression and release
schedules, as well as marketing spin. In the public eye, generations are
roughly marked by significantly improved and commercially successful designs.
Itanium is the brand name for 64-bit Microprocessors that implement the Itanium
architecture. Intel has released two processor families using the brand: Itanium
and Itanium 2.
Generation
|
Years
|
Prominent CPUs
|
1
|
1978-1982
|
|
2
|
1982-1986
|
|
3
|
1986-1989
|
|
4
|
1989-1993
|
|
5
|
1993-1997
|
|
1997-1999
|
||
6
|
||
1999-2001
|
||
7
|
||
2001-2003
|
||
8
|
2003-2007
|
6. Summary
Today we have discussed the
overview of 8085 and the generation of x86 microprocessors.
Lecture #2
1. Synopsis
·
Introduce the architecture of 8086
2. Target
By this
lecture, you should be able to answer the following questions
a)
Give the internal architecture of 8086?
b)
What is the advantage of 8086 over 8085?
3. Introduction
The 8086 introduced the reign
of the Intel 80x86 microprocessor family. Despite its design based on the
previous 8-bit processors (e.g. the 8080 and the 8085), the 8086 is not
entirely compatible with its predecessors. The 8086, the first widely used
16-bit microprocessor has been used to power the first IBM PCs.
4. Revision/Prerequisites
Please refer to the text Microprocesor
architecture of Remesh Gaonkar-Fifth Edition and the pages 1-7 of Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
Architecture
The 8086 have a microprogrammed
sequencer, but have also many wired functionalities such as to optimise the
size of the microcode. The vertical microinstructions are 21-bit wide. The
microprogram ROM contains 504 microinstructions. The 8086 have two functional
units aimed to work in parallel: the BIU (Bus Interface Unit) and the EU
(Execution Unit)
Execution Unit
The arithmetic and logic unit may
be loaded from three temporary registers (TMPA, TMPB, TMPC) and execute
operations on bytes or 16-bit words. The result of an operation may be stored
into one the temporary registers, or into any one of the 16-bit registers
connected to the internal data bus. These registers consist in four general
registers called AX, BX, CX and DX, two stack pointers (SP and BP), and two
index registers (SI and DI).
Bus Interface Unit
The bus interface unit is
intended to compute the addresses. This unit is made of two temporary registers
used by indirect addressing, four segment registers (DS, CS, SS
and ES), a program counter (IP - Instruction Pointer), and a
6-byte stack to store the pre-fetched opcodes and data.
6. Summary
Today we have discussed the
overview of 8085 and a detailed description of 8086 architecture. 8086 has two
functional units BIU and EU. BIU performs address computation while the EU
execute the operation.
7. Exercise Questions
1.
The 8086 processor addresses --------- bytes of memory.
2.
Memory above 1M byte is called --------- memory.
3.
What are program visible registers?
Lecture #3
1. Synopsis
·
Detailed study of 8086 microprocessor
·
BIU and EU
2. Target
By this
lecture, you should be able to answer the following questions
a)
Explain the
segment registers of 8086?
b)
What is the necessity of instruction queues?
c)
What is a stack register? How it can be initialized?
3. Introduction
Today
we are going to see the details of 8086 microprocessor. It includes the components of EU and BIU and
also have to see the function of flag register.
4. Revision/Prerequisites
Please refer to the pages 1-7 of Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
Execution Unit
Segment Registers
Within
the 1 MB of memory space the 8086 defines four 64K-byte memory blocks called
the code segment, stack segment, data segment, and extra segment. Each of these
blocks of memory is used differently by the processor.
The
code segment holds the program instruction codes. The data segment stores data
for the program. The extra segment is an extra data segment (often used for
shared data). The stack segment is used to store interrupt and subroutine
return addresses.
The
concept of the segmented memory is a unique one. Older-generation
microprocessors such as the 8-bit 8086 or Z-80 could access only one 64K-byte
segment. This mean that the programs instruction, data and subroutine stack all
had to share the same memory. This limited the amount of memory available for
the program itself and led to disaster if the stack should happen to overwrite
the data or program areas.
The
four segment registers (CS, DS, ES, and SS) are used to "point" at
location 0 (the base address) of each segment. The segment registers are only
16 bits wide, but the memory address is 20 bits wide. The BIU takes care of
this problem by appending four 0's to the low-order bits of the segment
register. In effect, this multiplies the segment register contents by 16.
The point to
note is that the beginning segment address is not arbitrary -it must begin at
an address divisible by 16. Another way if saying this is that the low-order
hex digit must be 0.
Also note that
the four segments need not be defined separately. Indeed, it is allowable for
all four segments to completely overlap (CS = DS = ES = SS).
Memory locations
not defined to be within one of the current segments cannot be accessed by the
8086 without first redefining one of the segment registers to include that
location. Thus at any given instant a maximum of 256 K (64K * 4) bytes of
memory can be utilized. As we will see, the contents of the segment registers
can only be specified via S/W. As you might imagine, instructions to load these
registers should be among the first given in any 8086/88 program.
An
immediate advantage of having separate data and code segments is that one
program can work on several different sets of data. This is done by reloading
register DS to point to the new data. Perhaps the greatest advantage of
segmented memory is that programs that reference logical addresses only can be
loaded and run anywhere in memory. This is because the logical addresses always
range from 00000h to 0FFFFh, independent of the code segment base. Such
programs are said to be relocatable, meaning that they will run at any location
in memory. The requirements for writing relocatable programs are that no
references be made to physical addresses, and no changes to the segment
registers are allowed
Instruction Byte Queue
Instruction queue is
6 bytes long, FIFO structure. The instructions from the queue are taken for
decoding sequentially. Once a byte is decoded, the queue is rearranged by
pushing it out and the queue status is checked for the possibility of the next
opcode fetch cycle. While the opcode is fetched bus interface unit, the
execution unit executes the previously decoded instruction concurrently. The
microprocessor does not perform the next fetch instruction till at least two
bytes of the instruction queue are emptied.By prefetching the instruction there
is a considerable speeding up in instruction execution in 8086. This scheme is
known as instruction pipelining.
Bus Interface Unit
Buses and operation
Address Bus - 20-bit address bus.
Can access 220 memory locations i.e 1 MB of memory.
Data Bus - 16 bit data bus. Can
access 16 bit data in one operation. (All registers of the 8086 are 16 bits
wide, further contributing to the moniker of "16-bit
microprocessor".)
Control buses - Carries the
essential signals for various operations.
8086 instructions varied from 1 to
6 bytes. However, fetch and execution were concurrent; the Bus Interface Unit
fed the instruction stream to the Execution Unit through a 6 byte prefetch
queue, a form of loosely coupled pipelining.
6. Summary
Today we have discussed the
overview of 8085 and a detailed description of 8086 architecture. 8086 has two
functional units BIU and EU. BIU performs address computation while the EU
execute the operation.
7. Exercise Questions
a) Which register holds the
count for some instructions?
b) Which segment register is
used to store the interrupt and subroutine return address registers?
Lecture #4
1. Synopsis
·
Detailed study of 8086 microprocessor
·
Registers
2. Target
By this
lecture, you should be able to answer the following questions
a)
Explain the
General purpose registers of 8086?
b)
What is a flag register?
c)
What is a stack register? How it can be initialized?
3. Introduction
Today
we are going to see the general purpose registers and other special purpose
registers available in 8086 processor.
4. Revision/Prerequisites
Please refer to the pages 1-7 of Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
General Purpose Registers
All general registers of the 8086
microprocessor can be used for arithmetic and logic operations. The general
registers are:
a) Accumulator
Accumulator
register consists of 2 8-bit registers AL
and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains
the low-order byte of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations and string manipulation.
b) Base register
Base register
consists of 2 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of
the word, and BH contains the high-order byte. BX register usually contains a
data pointer used for based, based indexed or register indirect addressing.
c) Count register
Count register consists of 2 8-bit registers CL and CH,
which can be combined together and used as a 16-bit register CX. When combined,
CL register contains the low-order byte of the word, and CH contains the
high-order byte. Count register can be used as a counter in string manipulation
and shift/rotate instructions.
d) Data register
Data register consists of 2 8-bit registers DL and DH,
which can be combined together and used as a 16-bit register DX. When combined,
DL register contains the low-order byte of the word, and DH contains the
high-order byte. Data register can be used as a port number in I/O operations.
In integer 32-bit multiply and divide instruction the DX register contains
high-order word of the initial or resulting number.
The following registers are both general and index
registers:
·
Stack Pointer (SP) is a 16-bit register pointing
to program stack.
·
Base Pointer (BP) is a 16-bit register pointing
to data in stack segment. BP register is usually used for based, based indexed
or register indirect addressing.
·
Source Index (SI) is a 16-bit register. SI is used for indexed,
based indexed and register indirect addressing, as well as a source data
address in string manipulation instructions.
·
Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing, as well as a
destination data address in string manipulation instructions.
Other registers:
·
Instruction Pointer (IP) is a 16-bit register.
·
Flags is a 16-bit register containing 9 1-bit flags:
Overflow Flag (OF) - set if the result is too large positive
number, or is too small negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation
instructions will auto-decrement index registers. If cleared then the index
registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables
maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt
will occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the
result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or
borrow to bits 0-3 in the AL
Parity Flag (PF) - set if parity (the number of "1"
bits) in the low-order byte of the result is even.
Carry Flag (CF) - set if there was a carry from or borrow to
the most significant bit during last result calculation.
6. Summary
Thus the 8086 processor
consist of four 16 bit general-purpose registers and index registers. It also
provides a 16 bit flag register to keep up the status of operation.
7. Exercise Questions
1.
What is the purpose of segment
register in real mode addressing mode?
2.
The stack memory is addressed by
combination of the -------- segment plus ------- offset.
3.
If the base pointer (BP) addresses
memory, the --------- segment contains the data.
Lecture #5
1. Synopsis
·
Detailed study of 8086 microprocessor
·
Difference between 8086 and 8088
2. Target
By this
lecture, you should be able to answer the following questions
a)
What are main differences between 8086 and 8088
microprocessors?
3. Introduction
The
first x86 processor was developed in 1979 by Intel and was called the 8088.
This processor then went through six different generations.
4. Revision/Prerequisites
Please refer to the pages 1-7 of Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
8086 and 8088
The main difference between 8086 and 8088 microprocessors
are:
The BIU in 8088 is 8-bit data bus & 16- bit in
8086.Instruction queue is 4 byte long in 8088and 6 byte in 8086.
The 8088 and the 8086 could run the same programs but one
couldn't fit into the other's socket. The 8086 got its success mainly from the
IBM-PC although IBM preferred implementing the 8088 into its computers because
it was less expensive and less complex. Depending on the manufacturer, the 8086
and 8088 processors would run at a speed ranging from 4MHz to
16MHz.
8086
Clock speeds: 5 MHz (0.33 MIPS)
8 MHz (0.66 MIPS)
10 MHz (0.75 MIPS)
Bus width: 16 bits
Addressable memory: 1 Megabyte
Typical use: Portable computing
Ten times the performance of the 8080
8088
Clock speeds: 5 MHz (0.33 MIPS)
8 MHz (0.75 MIPS)
Internal architecture: 16 bits
External bus width: 8 bits
Typical use: Standard microprocessor for all IBM PCs and PC
clones
Identical to 8086 except for its 8 bit external bus
6. Summary
Thus we have seen the main
difference between 8086 and 8088 microprocessors.
Lecture #6
1. Synopsis
·
Addressing modes of 8086
2. Target
By this
lecture, you should be able to answer the following questions
a)How the physical address can be
generated from effective address?
b)
What are the logical instructions available for 8086?
Explain.
3. Introduction
The last day
we completed the registers available in 8086. Today we are going to see the
instruction sets and addressing modes of 8086.
4. Revision/Prerequisites
Please refer to the Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
Instruction Set
8086 instruction
set consists of the following instructions:
1. Data moving instructions.
Arithmetic - add, subtract, increment, decrement, convert
byte/word and compare.
Logic - AND, OR, exclusive OR, shift/rotate and test.
String manipulation - load, store, move, compare and scan for
byte/word.
Control transfer - conditional, unconditional, call
subroutine and return from subroutine.
2. Input/Output instructions.
3. Other - setting/clearing flag bits, stack operations,
software interrupts, etc.
Addressing modes
Addressing modes indicate a
way of locating data or operands. An addressing mode specifies how to calculate
the effective memory address of an operand by using information held in registers and/or constants contained within a
machine instruction. It describes the
type of operands and the way they are accessed for execution of an instruction.
1) Direct (Displacement only) Addressing Mode
The most common addressing mode is the displacement-only (or direct)
addressing mode. In this addressing mode, a 16-bit memory address (offset) is
directly specified as part of the instruction..
The instruction MOV
AL, DS:[8088H] loads the ALMOV [1234H], DS:DL stores
the value in the DL register to memory location 1234H.
The
displacement-only addressing mode is perfect for accessing simple variables.
By default, all
displacement-only values provide offsets into the data segment. If we want to
provide an offset into a different segment, we must use a segment override
prefix before the address. For example, to access location 1234H in the extra
segment (ES) we would use an instruction of the form MOV AX, ES:[1234H]
. Likewise, to access this location in the code
segment we would use the instruction MOV AX, CS:[1234H]. The DS:
prefix in the previous examples is not a segment override.
2)
Immediate
addressing mode
In
this type of addressing, immediate data is a part of instruction, and appears
in the form of successive byte or bytes.
Eg: MOV AX,0005H
Here 0005H is an
immediate data. The data can be 8 bit or 16 bit.
3)
Register
addressing mode
In
register addressing mode, the data is stored in a register and it is referred
using the particular register. All the registers, except IP can be used for
this purpose.
Eg:
MOV AX, BX
4)
The Register Indirect Addressing Modes
Sometimes, the
address of the memory location that contains data or operand is determined by
in an indirect way using the offset registers. This mode of addressing mode is
known as register indirect addressing mode. Here, the offset address of data is
in either BX or SI or DI
There are four forms of this addressing mode
on the 8086, best demonstrated by the following instructions:
mov al, [bx]
mov al, [bp]
mov al, [si]
mov al, [di]
Note: the
[si]
and [di] addressing modes work exactly the same way, just
substitute si and di for bx
above.
6. Summary
Thus the 8086 processor mainly
consist of 8 addressing modes. By this
lecture we know how to use the memory and we will continue the rest of this
section in the next class.
8. Exercise Questions
1.
What special symbol is sometimes
used to represent immediate data?
2.
Suppose that DS= 0200H, BX= 0300H,
and DI=400H. Determine the memory address accessed by each of the following
instruction.
a)
MOV AL, [1234H]
b)
MOV [DI], AL
3.
Which base register addresses data
in stack segment?
4.
What are the three program memory
addressing modes?
Lecture #7
1. Synopsis
·
Continuation of Addressing modes of 8086
2. Target
By this
lecture, you should be able to answer the following questions
a)
Explain the difference between Register-indirect and
indexed addressing modes?
b)
How the effective address is calculated in Based
indexed addressing mode?
3. Introduction
The last day
we started the addressing modes of 8086. Today we will see the rest of the
addressing modes of 8086.
4. Revision/Prerequisites
Please refer to the Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
Addressing modes
5)
Indexed
Addressing Modes
In
this mode of addressing, offset of the operand is stored in one of the index
registers. DS and ES are the default segments for index registers SI and DI
respectively.
The indexed addressing modes use the following syntax:
mov al, disp[bx]
mov al, disp[bp]
mov al, disp[si]
mov al, disp[di]
If
bx contains
1000h, then the instruction mov cl,20h[bx] will load cl from memory location ds:1020h.
Likewise, if bp
contains 2020h, mov
dh,1000h[bp] will load dh from location ss:3020.
We may substitute
6) Register Relative
si or di in the figure above
to obtain the [si+disp] and [di+disp] addressing
modes.6) Register Relative
In
this addressing mode, the data is available at an effective address formed by
adding an 8-bit or 16-bit displacement with the content of any one of the
registers BX, BP, SI and DI. in the default segment.
Eg:
MOV AX, 50H[BX]
The effective address is given as 10H * DS +
50H + [BX]
7) Based Indexed Addressing Modes
7) Based Indexed Addressing Modes
The based indexed addressing
modes are simply combinations of the register indirect addressing modes. The
effective address is calculated by adding the content of base register (
bx or bp) to the content of
an index register (si
or di).
Eg: MOV AX, [BX] [SI]
Effective address is computed as 10H * DS + [BX] + [SI]
The allowable forms for these
addressing modes are
mov al, [bx][si]
mov al, [bx][di]
mov al, [bp][si]
mov al, [bp][di]
Suppose that
bx
contains 1000h and si
contains 880h. Then the instruction mov al,[bx][si]
would load
The addressing modes that do not involve
al
from location DS:1880h. Likewise, if bp contains 1598h and di contains 1004, mov ax,[bp+di] will
load the 16 bits in ax
from locations SS:259C and SS:259D.The addressing modes that do not involve
bp use the data segment by default. Those that
have bp as
an operand use the stack segment by default.
By substituting
di in the figure above, we can obtain the [bx+di] addressing mode.
We substitute
di in the figure above for the [bp+di] addressing mode.
8) Based Indexed Plus Displacement Addressing Mode
These addressing modes
are a slight modification of the base/indexed addressing modes with the
addition of an eight bit or sixteen bit constant. The following are some
examples of these addressing modes:
mov al, disp[bx][si]
mov al, disp[bx+di]
mov al, [bp+si+disp]
mov al, [bp][di][disp]
di
may be substituted in the figure above to produce the [bx+di+disp] addressing
mode.
Suppose
bp
contains 1000h, bx
contains 2000h, si
contains 120h, and di
contains 5. Then mov
al,10h[bx+si] loads al from address DS:2130; mov ch,125h[bp+di]
loads ch
from location SS:112A; and
mov bx,cs:2[bx][di] loads bx from location CS:2007.
6. Summary
Today we have completed all
addressing modes used in 8086 programming.
9. Exercise Questions
1. Logic calculations are done in which type of registers?
2.
Suppose that DS= 1200H, BX= 0100H,
and DI=0400H. Determine the memory address accessed by each of the following
instruction.
a.
MOV [100H], DL
b.
MOV DL, [BX + 100H]
c.
MOV [SI + 100H], EAX
Lecture #8
1. Synopsis
·
Program addressing modes
·
Program, Data and Stack memory
2. Target
By this lecture,
you should be able to answer the following questions
a) How the addressing modes are differentiated?
3. Introduction
There are two
addressing modes for the control transfer instructions, intra segment and inter
segment-addressing modes. These addressing modes depend upon whether the
destination location is within the same segment or a different one the method
of passing the destination address to the processor.
4. Revision/Prerequisites
Please refer to the text Microprocesor
architecture of Remesh Gaonkar-Fifth Edition and the pages 38-40 of Advanced
microprocessors and peripherals, A K Ray & K M Chaudhari.
5. Concepts
Program
addressing modes
Program memory address can be of the
following three types
- Direct Program Memory addressing modes (JMP instructions- intersegment jump)
- Relative Program Memory Addressing modes (JMP instructions-intrasegment jumps)
- Indirect program memory accessing modes (CALL instructions)
Program, data and stack memories occupy the same memory
space. The total addressable memory size is 1MB KB. As the most of the
processor instructions use 16-bit pointers the processor can effectively
address only 64 KB of memory. To access memory outside of 64 KB the CPU uses
special segment registers to specify where the code, stack and data 64 KB
segments are positioned within 1 MB of memory.
Program memory
- program can be located anywhere in memory. Jump and call instructions can be
used for short jumps within currently selected 64 KB code segment, as well as
for far jumps anywhere within 1 MB of memory. All conditional jump instructions
can be used to jump within approximately +127 - -127 bytes from current
instruction.
Data memory - the
processor can access data in any one out of 4 available segments, which limits
the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra
segments can be usually done by prefixing instructions with the DS:, CS:, SS:
or ES: (some registers and instructions by default may use the ES or SS
segments instead of DS segment).
Word data can be located at odd or even byte boundaries.
The processor uses two memory accesses to read 16-bit word located at odd byte
boundaries. Reading word data from even byte boundaries requires only one
memory access.
Stack memory can be
placed anywhere in memory. The stack can be located at odd memory addresses,
but it is not recommended for performance reasons.
Intersegment
code
If the location to which control is to be
transferred lies in a different segment other than the current one, the mode is
called intersegment mode.
Intrasegment
mode
If the destination location lies in the
same segment, the mode is called intrasegment mode.
Intrasegment direct
Intrasegment
Modes
for control Intrasegment Indirect
Transfer
instructions Intersegment Direct
Intersegment
Intersegment Direct
Intrasegment
Direct Mode
In
this mode, the address to which the control is to be transferred lies in the
same segment in which the control transfer instruction lies and appears
directly in the instruction as an immediate displacement value. In this mode,
the displacement is computed relative to the content of the instruction pointer
IP.
The effective address to which control is
transferred is given by the sum of 8 or 16 bit displacement and current content
of IP. In case of jump instruction, if the signed displacement (d) is of 8 bits
(-128
Lecture #9
Intra segment
Direct Mode
In this mode the displacement to which the
control is to be transferred is in the same segment in which the control
transfer instruction lies, but it is passed to the instruction indirectly.
Here, the branch instruction is found as the content of register or a memory
location. This addressing mode may be used in unconditional branch
instructions.
Intersegment
Direct Mode
In this mode, the address to which the
control is to be transferred is in a different segment. The addressing mode
provides a means of branching from one code segment to another code segment.
Here the CS and IP of the destination address are specified directly in the
instruction.
Intersegment
Indirect Mode
In this mode, the address to which the
control is to be transferred is in a different segment and it is passed to the
instruction indirectly, i.e contents of a memory block containing four bytes, i.e
IP(LSB), IP(MSB), CS(LSB) and CS(MSB).The starting address of the memory block
may be referred using any of the addressing mode, except immediate..
6. Summary
Today we have discussed the
other addressing modes.
7. Exercise Questions
1. Which addressing mode is
used in unconditional branch instructions?
2.
What is the addressing
mode used in which the destination location is in a different segment?
3.
What is the difference
between intrasegment and intersegment addressing modes?
Lecture #9
1. Synopsis
·
Segmented Memory
·
Physical address calculation
2. Target
By this
lecture, you should be able to answer the following questions
a) What linear address is corresponding to a particular
segment/offset address?
3. Introduction
A
processor requires a minimum of 20 address lines to have the ability to access
1MB of memory. But the problem is 20 bit addresses are too big to fit in 16 bit
registers. And the solution to this problem is Memory Segment.
4. Revision/Prerequisites
Please refer to the text Microprocessors
architecture of Remesh Gaonkar-Fifth Edition and Advanced microprocessors and
peripherals, A K Ray & K M Chaudhari.
5.
Concepts
Memory Organization
Address Bus:
The address bus is multiplexed
with data bus.
20-bit memory address --->
Access 1 MiB of
segmented memory space. (220 = 1,048,576)
16-bit I/O address
----------> Access 64 KiB
of separate I/O space. (216 = 65,536)
Data Bus:
The data bus is multiplexed with address bus. The 16
bit data bus, transfers 16 bits of data in a single operation. All internal
registers are also 16 bits wide.
The 8086 is therefore a TRUE
16-bit processor.
The Total address space is theoretically 1
MiB + 64 KiBs, but the maximum linear address space is only 64 KiBs,
because of internal address segmentation , also each physical address location
can be addressed by 4096 distinct segment: offset combinations.
Segmented Memory Architecture (Real Mode)
As you already
know, a processor requires a minimum of 20 address lines to have the ability to
access 1MB of memory. Each byte in memory has a 20 bit address starting with 0
to 220-1
or 1 meg of addressable memory. So the addresses are expressed as 5 hex digits
from 00000 – FFFFF.
But the problem
is: 20 bit addresses are TOO BIG to fit
in 16 bit registers. And the solution to this problem is Memory Segment. That
is dividing the address space into 64KB segments and coordinates memory access
through the use of two 16 bit values - a Segment and an Offset.
The segment
numbers range from 0000 to FFFF. Within a segment, a particular memory location
is specified with an offset. An offset also ranges from 0000 to FFFF.
Figure 1: Real Mode Translation Process
Four dedicated Segment
Registers were created in order to hold the segment portion of the
processor generated addresses. Each of these registers was designated to serve
as a base pointer to a unique segment in the processor physical address space.
Segment Register
|
Designated Role
|
CS
|
Code Segment Register This register points to the
currently active code segment. Used in conjunction with the IP register to
point to the next instruction to be fetched and executed by the processor.
|
DS
|
Data Segment Register This register usually points to the default data
segment which contains the global and static variables of the active
application.
|
ES
|
Extra Segment Register General purpose segment register used mostly for
data transfers between different segments.
|
SS
|
Stack Segment Register
This register points to the segment containing the active stack. The top of stack is located at address SS:SP. |
FS
GS |
General Purpose Segment Registers
First introduced on the 80386, these segment registers can be used for any purpose in your application code. |
Table 1 - Segment
registers on the 80x86 processors
The
value set into a segment register identifies a specific 64KB region of memory,
whereas the offset part points to an exact location within that region. To
calculate a physical address, the processor shifts the content of the segment
register four bits to the left (thus multiplying its value by 16) and adds the
offset.
physical address =
segment×16 + offset
Figure 2: Physical Memory Calculation
Since the content of a segment
register forms the 16 high-order bits of a physical address, it is always
divisible by 16 and has its lowest four bits set to zero. It can be depicted as
in the following figure:
Figure 3: Consecutive segments
For years, the
world of personal computing was dominated by real-mode MS-DOS. The arrival of
the Windows operating system which dispensed with real-mode in favor of the
much advanced protected-mode, marked a new era in the computing industry.
6. Summary
Today we have discussed the
memory organization of 8086 microprocessor.
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